Field of the Invention
The invention relates to a circuit for testing integrated circuits on a wafer using a test apparatus, a test structure and a method for this purpose. In particular, the invention relates to a method for testing integrated circuits on a wafer.
During their manufacture, semiconductor chips are subjected to a plurality of test methods. The test methods are essentially distinguished by front-end test methods and back-end test methods. The essential difference between the two separate test procedures is that, in the case of front-end test methods, the tests are carried out while the integrated circuits are still unseparated from the wafer, i.e. the wafer has not yet been sawn up into individual chips. In the case of back-end test methods, the individual chips are actually tested separately. The task of the front-end test method is, among other things, to carry out a first operational test for the integrated circuits on the wafer and to find faults. Some of the faults can be eliminated by a subsequent laser process by severing xe2x80x9chard fusesxe2x80x9d, that is to say special fuses, using a laser and thereby replacing the faulty circuit regions with redundant circuits already provided on the chip. Such a laser process, also called laser trimming, needs to be carried out before the integrated circuits on the wafer are cut up into chips, because aligning individual chips in the laser apparatus creates considerable difficulties and would thus be very time-consuming and cost-intensive. By contrast, severing the hard fuses in an integrated circuit on the wafer that has not been sawn up is comparatively easy to do. For this reason, it is necessary to find out in the actual front-end test method which hard fuses mounted on the respective integrated circuit need to be severed in the subsequent laser process.
Particularly where reference voltages are produced internally in the chip, the manufacturing process results in fluctuations in the reference voltage produced from chip to chip. The fluctuations become particularly noticeable in the case of analog voltages because these small discrepancies from the reference value can have considerable effects on the operation of the circuit. Analog reference voltages can therefore move only within a certain tolerance range or need to be suited to the operation of the entire component. Whereas, previously, integrated circuits in which the reference voltage differed from the required voltage by more than a particular percentage were regarded as rejects, practice has now been changed to making the reference voltage settable on the respective chip, in order thus to obtain a virtually identical functionality for each individual chip. The setting of the reference voltage is effected using the laser trimming process described above.
The previous method of applying such a reference voltage externally during the operational tests to the circuit to be tested has the drawback that, between the externally applied voltage source and the contact on the integrated circuit, a voltage drop occurs which cannot be foreseen on account of the unknown currents which flow. Since, however, it is desirable to test the integrated circuits under the conditions of their later operation as far as possible, to which end the analog reference voltage potentials need to be applied appropriately inside the integrated circuit during testing, it is advantageous for the reference voltage to be provided internally in the chip for the actual front-end testing.
This now requires that the integrated circuit be set individually in the actual front-end test method, i.e. it is necessary to find out which of the hard fuses in an integrated circuit are severed in the later laser trimming process, and which are not. However, for reasons of throughput, conventional front-end test apparatuses always test a plurality of integrated circuits on a wafer at the same time and, in this context, supply each of the circuits with the same test pattern.
The test procedure first establishes which of the hard fuses need to be severed for the optimum setting in a subsequent laser process. Next, xe2x80x9csoft fusesxe2x80x9d are set. The soft fuses are memory cells that simulate the operation of the hard fuses during the test procedure in the integrated circuit. The settings then start the actual test method. In conventional test apparatuses, such setting of the soft fuses respectively affects all of a test run""s integrated circuits connected in parallel. Individual setting is not possible, because the individual circuits cannot be addressed separately from one another by the test apparatus. However, it is usually possible for supply voltages supplying the individual integrated circuits to be turned on individually in conventional test apparatuses. Since the amount of time required for testing a chip is relatively great (approximately 30 minutes), it is not feasible, for reasons of economic viability, to set and test the chips successively.
It is accordingly an object of the invention to provide an integrated circuit, a test structure and a method for testing integrated circuits which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which it is possible, before a parallel operational test for a plurality of integrated circuits on a wafer, to be able to make individual settings for parameters in the circuits to be tested.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit containing memory cells for storing test parameters; and an electronic circuit for carrying out an operational test and connected to the memory cells. The electronic circuit applies an operating signal and permits a single write operation to the memory cells and prevents any further writing to the memory cells.
The invention provides a circuit that has an electronic circuit as an aid to carrying out an operational test. The operational test is carried out by a test apparatus. Connected to the test apparatus are a plurality of integrated circuits which are supplied with test patterns in parallel and whose supply voltages can be applied individually by the test apparatus. The integrated circuit contains memory cells, for storing test parameters, which can have information written to them by the test apparatus and on which the operation of the respective integrated circuits depends. To prevent the memory cells in the connected integrated circuits from each receiving the same content, the invention provides that, once an operating signal, preferably a supply voltage, has been applied to the integrated circuit by the circuit, a single write operation to the memory cells is permitted, and thereafter further writing to the memory cells is prevented. This makes it possible for the integrated circuits to be successively provided with their individual settings as a result of writing to memory cells, without memory cells which have already had information written to them being overwritten.
The invention also provides a test structure having a test apparatus to which a plurality of such integrated circuits are connected. The test apparatus is able to turn the supply voltages for the integrated circuits on and off individually, which allows an individual response from the individual integrated circuits as a result of applied test patterns.
The inventive method involves ascertaining the parameters to be set in a preliminary test after the supply voltage to a first integrated circuit has been turned on. On the basis of the parameters obtained, memory cells in the first integrated circuit have information written to them. After that, the supply voltage is applied to a next integrated circuit, a preliminary test is carried out, and memory cells have information written to them on the basis of the parameters obtained. This is carried out until the parameters have been set for all the connected integrated circuits. Next, the actual operational test is then carried out by the test apparatus for all the integrated circuits in parallel. Therefore, for the actual first operation test, the integrated circuits are placed into an operating mode, in which they are actually operated in their later application.
In one advantageous refinement, provision may be made for the electronic circuit to have an input and an output, the input receiving a control signal for writing to the memory cells. The control signal at the input is transmitted to the output for the single write operation to the memory cells and is then blocked so long as the supply voltage is applied to the electronic circuit. This assures the single write operation to the memory cells by virtue of a Write-Enable signal for the memory cells concerned being applied to the appropriate inputs of the memory cells, or isolated therefrom. Since information can be written to the memory cells only when a Write-Enable signal is applied, this ensures that information can be written to the memory cells only once, namely after a supply voltage has been applied and the Write-Enable signal has subsequently been applied.
In one preferred embodiment, the electronic circuit has a flipflop, a pulse generator and a gate. The gate is connected such that it transmits or does not transmit a control signal at its input on the basis of the output signal from the flipflop. The flipflop is connected such that it adopts a first state after the supply voltage has been turned on, and changes to a second state when the pulse generator connected to one input of the flipflop outputs a pulse to the flipflop as a result of a control signal applied to the input of the pulse generator. This advantageously ensures that the control signal, i.e. the Write-Enable signal for the memory cells, is not forwarded to the memory cells as soon as a control signal has actually been applied to the memory cells. In addition, the additional complexity for such a circuit is very low and can easily be integrated into an existing control signal line by use of the gate.
Preferably, another provision may be for the integrated circuit to have severable lines, the memory cells simulating the operation of the severed or unsevered lines. The severable lines are xe2x80x9chard fusesxe2x80x9d, which can make permanent settings to the integrated circuits, e.g. in a laser trimming process. Severing or not severing the lines cannot be used to make settings during the actual operational test, however, since these settings are irreversible and therefore permit no further change to the set parameters. To be nevertheless able to test the integrated circuits, during an operational test, in the manner in which they are operated in their later application, their operation can be simulated by the memory cells as though coding of the severable lines, i.e. the action in a laser process, had already taken place. Therefore, these memory cells can have settings written to them that have previously been found out in a preliminary test, and these settings can be changed as required should they prove not to be optimum.
In another advantageous refinement, provision may be made for the memory cells to be used to set an internal reference voltage. In this case, by way of example, the memory cells form a reference voltage source in connection with an integrated digital/analog converter. Since the properties of the digital/analog converter, e.g. individual voltages, differ from one another on account of process-related discrepancies, a preliminary test makes it possible to find out the optimum setting of the memory cells at which the internal reference voltage corresponds to the desired voltage, or at which the internal reference voltage achieves the desired operation in the integrated circuit.
In accordance with another preferred embodiment, such integrated circuits can be connected to a test apparatus that can turn the supply voltages for the integrated circuits on or off individually. This advantageously ensures that the preliminary test used to determine the individual parameters of the integrated circuit can be carried out individually for each circuit. This makes it possible to save time when determining the parameters, since the preliminary test does not need to perform any standard routines, but instead individually matched program procedures geared to the operation obtained by the parameters.
In another advantageous embodiment, a plurality of integrated circuits connected in parallel are connected to the outputs of the test apparatus. The integrated circuits are tested using identical test patterns, which allows the operation test to be carried out in parallel and thus with a great time saving.
Preferably, provision may be made for the test apparatus to supply the supply voltage successively to the integrated circuits connected in parallel. Each of the integrated circuits already supplied thus remains supplied with the supply voltage until completion of the operation test. In this way, the connected integrated circuits can be addressed individually in order to carry out the preliminary test, i.e. in order to determine the parameters and to write the parameters to the memory cells. Once the preliminary test has been carried out for a particular integrated circuit, the supply voltage needs to continue to be applied so that the settings stored in the memory cells are maintained.
In one preferred embodiment of the inventive method, the individual parameters determined by a preliminary test are written by successively turning on the supply voltage on one of the circuits and then writing the respective parameters to the memory cells. This is carried out until all the connected integrated circuits have been set. In one preferred embodiment, the individual parameters can be determined iteratively. In this context, after turning on a supply voltage on one of the integrated circuits, arbitrary or prescribed parameters are first written to the memory cells and are then checked on the basis of particular test patterns to determine whether the optimum operation of the integrated circuit has been achieved. This procedure is repeated, by suitably altering the parameters, until the parameters for the optimum operation of the integrated circuit have been found out. In this context, for each new write operation to the memory cells, it is necessary first to turn off the supply voltage and to turn it on again after a particular time, in order to erase the contents of the memory cells and to allow a new write operation. This ensures that the optimized parameters for each of the integrated circuits can be set individually.
Preferably, provision may also be made for the parameters to be prevented from being written to the memory cells if information has already been written thereto by a preceding step. This has the advantage that, when different parameters are to be written to the memory cells, the memory cells in the circuit already described retain their contents.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit, a test structure and a method for testing integrated circuits, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.